An Interconnect-Centric Design Flow for Nanometer Technologies

As the integrated circuits (ICs) are scaled into nanometer dimensions and operate in giga-hertz frequencies, interconnect design and optimization have become critical in determining system performance and reliability. This paper presents the ongoing research effort at UCLA to develop an interconnect-centric design flow, including interconnect planning, interconnect synthesis, and interconnect layout, which allows interconnect design and optimization to be properly considered at every level of the design process. Efficient interconnect performance estimation models and tools at various levels are also being developed to support such an interconnect-centric design flow.